An Agile Systolic Array-Based Hardware Accelerator for Scalable Multi-Head Self-Attention

1月 1, 2025·

Xinyu Chen

Yu Li

Beining Zhao

Yintao Liu

Shan Cao

Zhiyuan Jiang

· 0 分钟阅读时长

引用 DOI

Authors

Xinyu Chen

M.S.

Authors

Yu Li

Ph.D.

Authors

Beining Zhao

M.S.

Authors

Yintao Liu

M.S.

Authors

Shan Cao

Associate Professor

Authors

Zhiyuan Jiang

Professor

---

← Agile Coverage for Low-Altitude Aerial Intelligent Networks: A Blended Hyper-Cellular Solution 1月 1, 2025

An Arbitrary Register Grouping Scheme for RISC-V Vector Extension: Compilation Support and Hardware Implementation 1月 1, 2025 →