AI Chips and Neural Network Processors
We focus on the design of Domain-Specific Architectures (DSA) for edge intelligence. By leveraging heterogeneous computing (RISC-V + NPU) and hardware-software co-design, we address the bottlenecks of power consumption and latency in modern deep learning deployment.
Our team has developed a series of accelerators ranging from ultra-low power NPUs to high-performance RISC-V vector processors, supported by a full-stack LLVM-MLIR compiler ecosystem.
Key Directions and Achievements
Heterogeneous RISC-V + NPU
A flexible heterogeneous architecture combining RISC-V control cores with specialized NPU acceleration units for efficient mixed-workload processing.
AI Compiler Stack (LLVM-MLIR)
An end-to-end compilation framework based on LLVM and MLIR, enabling automated operator mapping and optimization for our custom hardware.
Sparsity-Aware Acceleration
Hardware-level optimizations for sparse neural networks (e.g., AlexNet, VGG, ResNet) to maximize energy efficiency and throughput.