NeuroBaseband Energy-Efficient RISC-V Fusion Baseband

§0 · Key finding

Software flexibility, near-ASIC efficiency

High-efficiency RISC-V fusion computing wins real deployment efficiency through low idle power and system-level scheduling — compressing the 10³× GPP-to-ASIC efficiency gap to about 10×.

Baseband efficiency comparisons have long ignored one fact: peak throughput is not deployment efficiency. Venus v2 reaches 256 MSps/W on FFT (28nm-normalized), 33.4× the Xeon 6434. More decisive is the 0.027W idle power — under light load, idle power dominates average energy, and that is what real deployments pay for.

Software-flexible with ASIC-grade efficiency. High-efficiency RISC-V fusion computing wins real deployment efficiency through low idle power and system-level scheduling.

— ACELab · Deep Transcend, team deck STRATEGIC TAKEAWAY2026-09

ContextFusion baseband compresses the GPP↔ASIC efficiency gap to roughly 7–10× while keeping RISC-V open programmability.Why it mattersThe efficiency inflection shows up on real load curves, not on peak benchmarks.

§1 · Architecture thread

Four research threads, one cross-layer throughline

Pulled by the dataflow and periodicity of wireless baseband — domain-specific co-design from instruction set to system, while keeping RISC-V open programmability.

The vector unit decides operator efficiency, dataflow scheduling decides system real-timeliness, the domain toolchain decides ecosystem usability, and the low-power SoC decides deployed energy. The four are not parallel modules but projections of one dataflow throughline at different abstraction levels.

Vector unit

ARBITRARY REGISTER GROUPING · RVV+

Arbitrary register grouping matches vector length to the real length of wireless operators.

Beyond RVV's fixed power-of-two grouping: 64-bit extension encoding and conflict detection handle register overlap and read-write hazards; an element-exchange engine covers cross-lane shuffle and gather/scatter; complex/fixed-point divide and saturating ops run on extensible datapaths. Target operators: FFT · channel estimation · coding · linear algebra.

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Dataflow scheduling

HIERARCHICAL DATAFLOW SCHEDULING

Software handles global low frequency; hardware handles local high frequency — scalability meets real-time.

A task–thread–cluster three-level model: DAGs explicitly map baseband modules, hierarchical memory reinforces locality, and a pack-and-ship mechanism coordinates DMA/CSR/interrupt deployment and recycling. A hardware scheduler watches dependencies and output state to fire tasks fast, guaranteeing throughput and hard real-time.

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Toolchain

DSL → LLVM → RISC-V · SAME-SOURCE

One source of code runs through task description, compilation and hardware deployment.

A domain language describes task graphs and dependencies; LLVM performs instruction splitting/merging and arbitrarily-grouped register allocation, emitting RISC-V assembly mapped onto extensible datapaths. The same source supports simulation, evaluation and binary deployment — domain semantics survive all the way into the compiler and scheduling backend.

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Low-power SoC

POWER DOMAINS · MBIST

Four power domains wake stage by stage with load; industrial-grade testability.

Four operating modes — sleep, standby, digital front-end and compute — with an always-on domain for fast wakeup; concurrent multi-mode shares one compute cluster. MBIST and fault coverage deliver industrial testability, paving the road to automotive and base-station deployments.

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§2 · Measured evidence

LDPC decoding: near-x86 throughput at one to two orders less energy

Venus normalized throughput is about 89% of the Xeon's, at 4.15 nJ/bit/iter — 84.4× lower than ARM A76 and 181.8× lower than GPU 4090. Basis: CS4 · rate 340/1024 · block 25443 · single-core CPU throughput; throughput normalized linearly, energy quadratically, across process nodes.

LDPC decoding performance (28nm-normalized)

CLICK A ROW FOR BASIS & SOURCE · ASIC ACC100 AS REFERENCE FLOOR

Platform	Clock	Node	Mbps	nJ/bit/iter

Source · In-house · Venus v2 measured (K2) · 2026-09

Idle power: the underestimated driver of deployment energy

Base stations and edge nodes spend most of their time under light load. Venus v2 idles at 0.027W (single-Tile basis), two orders of magnitude below rivals; at the 99% load threshold total power is Venus ≈4.36W vs ACC100 ≥19.2W, and Venus is more efficient below 2.06 Gbps of throughput demand.

§3 · Silicon

Venus v2: from architecture to silicon

A multi-mode SoC at 40nm, 300MHz, 10 cores and four power domains, peaking at 0.763W. Four operating modes cover sleep, standby, digital front-end and compute, waking stage by stage with load; MBIST and fault coverage deliver industrial-grade testability.

Metric	Value	Note

Source · In-house · Venus v2 tape-out measurements (K4) · 2026-09

§4 · Position & ecosystem

An open fusion baseband for 6G AI-RAN

Open RISC-V ISA + domain extensions + a same-source toolchain turn baseband from a black-box ASIC into evolvable infrastructure.

NeuroBaseband's open ecosystem lives on the ACE-Echo open platform: architecture documents, toolchain and evaluation environments are open, supporting one continuous path from academic research to customer integration. On track record, top-venue papers and repeated successful tape-outs close the loop of "said → built → measured".

Visit the ACE-Echo open platform →

Dimension	Fact	Note

Source · ACELab team deck p7 (K9) · 2026-09