数字大规模集成电路与 SoC
数字大规模集成电路设计、片上系统设计,以及面向通信与智能计算任务的硬件系统实现。
Personal Profile
曹姗,博士,上海大学通信与信息工程学院通信工程系副教授。2005年至2009年就读于清华大学电子科学与技术专业并获工学学士学位,2009年至2015年在清华大学电子科学与技术专业攻读博士学位。
2015年至2017年在北京理工大学信息与电子学院从事博士后研究工作;2017年至今任职于上海大学通信与信息工程学院,先后担任讲师、副教授。研究工作聚焦数字集成电路设计、领域定制计算架构、无线通信系统基带处理与深度学习硬件加速。
Research
数字大规模集成电路设计、片上系统设计,以及面向通信与智能计算任务的硬件系统实现。
面向并行计算、通信基带处理和专用计算任务的体系结构设计与优化。
无线通信系统、基带处理器、无线信道编译码器设计与高效实现。
神经网络加速芯片、模型压缩、网络模型轻量化及相关软硬件协同优化。
Honors & Service
上海市海外高层次人才计划
上海大学蔡冠深优秀青年教师
IEEE Circuits and Systems Society COMCAS Technical Committee Member
IEEE ISCAS Review Committee Member
ICTC 2022 Special Session Chair,IEEE SiPS 2019 Special Session Chair 等
Projects
Teaching
Fall 2022-2024
Spring 2020-2024
Spring 2019-2024
Fall 2016-2017
Selected Publications
[1] S. Cao, S. Chen, L. Jiang and Z. Jiang, “A Critical-Set-Based Multi-Bit Successive Cancellation List Decoder for Polar Codes: Algorithm and Implementation,” IEEE Transactions on Circuits and Systems I: Regular Papers, early access.
[2] Y. Li, S. Cao, B. Zhao, W. Zhang and Z. Jiang, “Hybrid-Grained Pruning and Hardware Acceleration for Convolutional Neural Networks,” IEEE ISCAS, 2024.
[3] B. Ruan, L. Jiang, S. Cao and Z. Jiang, “Dynamically Configurable FIR Filters Based on Serial MACs and Systolic Arrays,” IEEE ISCAS, 2024.
[4] F. Ye, F. Yuan, S. Cao, Z. Jiang and S. Zhou, “SPMD-Based Mixed-Radix FFT and Channel Estimation for Energy-Efficient O-RAN,” FCN, 2023.
[5] Y. Shen, F. Yuan, S. Cao, Z. Jiang and S. Zhou, “Parallel Computing for Energy-Efficient Baseband Processing in O-RAN,” GLOBECOM, 2023.
[6] M. Yang, S. Cao, W. Zhang, Y. Li and Z. Jiang, “Loop-Tiling Based Compiling Optimization for CNN Accelerators,” ASICON, 2023.
[7] W. Zhang et al., “An FPGA-based Low Latency Sensing and Communication Platform for Collaborative Autonomous Driving,” SPAWC, 2023.
[8] S. Cao, H. Hu, L. Jiang, etc., “A Domain Specific Computing Architecture for Open 6G Baseband Signal Processing,” ACM TURC, 2023.
[9] R. Jiang, Z. Fei, S. Cao, etc., “Deep learning-aided signal detection for two-stage index modulated universal filtered multi-carrier systems,” IEEE Transactions on Cognitive Communications and Networking, 2022.
[10] Q. Sun, S. Cao, and Z. Chen, “Filter Pruning via Automatic Pruning Rate Search,” ACCV, 2022.
[11] L. Hui, S. Cao, Z. Chen, S. Li and S. Xu, “Configurable CNN Accelerator in Speech Processing based on Vector Convolution,” AICAS, 2022.
[12] C. Zhang, H. Hu, S. Cao and Z. Jiang, “A Novel Blind Detection Method and FPGA Implementation for Energy-Efficient Sidelink Communications,” SiPS, 2021.
[13] A. Nahli, S. Cao, Z. Jia, R. Ma and S. Xu, “Dataset and Network Structure: Towards Frames Selection for Fast Video Deblurring,” IEEE Access, 2021.
[14] H. Wang, S. Cao and S. Xu, “A Real-Time Face Recognition System by Efficient Hardware-Software Co-Design on FPGA SoCs,” AICAS, 2021.
[15] S. Cao, L. Jiang, T. Lin, S. Zhang and S. Xu, “A Semi-Folded Decoding Architecture for Flexible Codeword Length Configuration of Polar Codes,” ISCAS, 2021.
[16] S. Cao, T. Lin, S. Zhang, S. Xu and C. Zhang, “A Reconfigurable and Pipelined Architecture for Standard-Compatible LDPC and Polar Decoding,” IEEE Transactions on Vehicular Technology, 2021.
[17] S. Cao, W. Deng, Z. Bao, C. Xue, S. Xu and S. Zhang, “SimuNN: A Pre-RTL Inference, Simulation and Evaluation Framework for Neural Networks,” IEEE JETCAS, 2020.
[18] S. Cao, H. Zheng, T. Lin, S. Zhang and S. Xu, “An Unfolded Pipelined Polar Decoder With Hybrid Number Representations for Multi-User MIMO Systems,” IEEE TCAS II, 2020.
[19] Z. Jiang, Z. Cao, S. Fu, F. Peng, S. Cao, etc., “Revealing much while saying less: Predictive wireless for status update,” IEEE INFOCOM, 2020.
[20] H. Wang, S. Cao, S. Xu, etc., “Hardware-software co-design for face recognition on FPGA SoCs,” IEEE ISCAS, 2020.