Published 13 September 2026 · Silicon milestone
Our first-generation Venus chip has successfully taped out and achieved first light. Developed through the 5G-Lite project, the chip has completed packaging and evaluation-board bring-up, and successfully demonstrated NR cell search using real over-the-air signals. Its detected physical cell identity matched the commercial-network reference measurement.
This milestone brings together years of work on Echo’s communication software and the Venus programmable architecture—from algorithms and RTL to a working chip.
From design to packaged silicon
The team completed physical implementation, fabrication, wire bonding and packaging, then brought the chip up on its evaluation board. The resulting system runs application code and processes incoming radio signals.
| Chip and package | Details |
|---|---|
| Device | DT-VENUS-A1 AI-RAN SoC |
| Package | HLQFP128B |
| Package body | 14 × 14 mm |
| Pin count | 128 |
| Processing architecture | Configurable DFE, programmable Venus processor and task Scheduler |
| Clock and power organization | 3 PLLs and 4 power domains |
Real signals. A matching cell identity.
The silicon tests exercised the path from real radio input through DFE synchronization and Venus processing to cell-search results. The chip reported PCI 800 and SSB index 3. A Cellular-Pro measurement of the commercial NR network independently showed PCI 800, confirming that the detected physical cell identity was correct.
| Field | Chip output | Network reference |
|---|---|---|
| Physical cell identity (PCI) | 800 | 800 |
| SSB index | 3 | — |
| Network context | — | NR-SA · Band n1 · NR-ARFCN 426030 |
Successful bring-up and this over-the-air result validate the implemented NR cell-search path on silicon, connecting the programmable architecture to a real communication workload.
Low-power operation. Built for communication.
Venus combines configurable communication primitives with programmable processing and has demonstrated NR cell search on silicon. With its Cluster fully loaded, the evaluation board consumes 0.95 W excluding the DFE, providing a low-power computing foundation for radio monitoring, synchronization and edge communication applications.
Full Cluster load · Entire evaluation board, excluding DFE
ENERGY COMPARISON · NORMALIZED TO 28 nm
VENUS VS ARM
NEON
ENERGY EFFICIENCY
≈7.7×28 nm normalized calculation · Reference / Venus
RK3588 · Cortex-A76
VENUS VS INTEL
AVX-512
ENERGY EFFICIENCY
≈25.6×28 nm normalized calculation · Reference / Venus
Xeon 6434
Measurement scope: the entire development board for RK3588, CPU package power for Xeon, and the entire evaluation board with the Cluster fully loaded and DFE excluded for Venus. Both ratios are calculated from the single-core comparison data below, normalized to 28 nm.
Measurement scope and energy calculation
Power measurement.The ARM Cortex-A76 reference runs on RK3588, with power measured across the entire development board. Xeon 6434 uses CPU package power. Venus uses 0.95 W for its entire evaluation board with the Cluster fully loaded, excluding the DFE. In the single-core comparison, CPU idle power is apportioned by physical core count.
Workloads and data.The CPU reference data comes from LDPC workloads: the RK3588 Cortex-A76 baseline uses NEON, and the Xeon 6434 baseline uses AVX-512. Venus uses an SSB processing workload. The Venus calculation is 0.95 W / 8.448 Mbps, yielding approximately 112.45 nJ/bit. The comparison results apply to these workloads and measurement scopes.
Process normalization.Energy is scaled using E₂₈ = E × (28 / L)², with process-node values of 8 nm for RK3588, 7 nm for Xeon 6434 and 40 nm for Venus. The normalized reference-to-Venus energy ratios are (34.58 × 12.25) / (112.45 × 0.49) ≈ 7.7 and (88.33 × 16) / (112.45 × 0.49) ≈ 25.6.
Bring your communication workload to Venus
Start with a cell-search or signal-processing example, then adapt its algorithm and dataflow to your application. ACE-Echo 1.0 lets you compile and simulate Venus applications and quickly explore approximate cycle-level performance before deploying to hardware.
Start developing with ACE-Echo 1.0 → · Explore the NR cell-search example →
Echo and Venus come together
Configurable DFE hardware handles front-end communication primitives, while the Venus processor and Scheduler execute programmable algorithms and coordinate tasks. The 5G-Lite silicon milestone gives our communication–AI architecture research a hardware foundation for developing and testing applications.
Opening application development
ACE-Echo 1.0 opens this development path with a Gem5-based simulator for Venus applications, approximate cycle-level performance evaluation and an initial Agent-assisted development framework.
Our ACE-Echo 2.0 roadmap builds toward intent-driven development: describe an application, and an Agent helps generate an implementation deployable on Venus.
Thank you to every project member and partner who contributed to the design, verification, fabrication and silicon testing of this first chip.