📜Venus: A RISC-V Domain Specific Architecture towards Integrated AI and Wireless Baseband Processing for 6G Edge Intelligence
We are proud to announce that our team’s research paper on the Venus architecture has been officially accepted by the IEEE Wireless Communications Magazine 🎉🎉. As a RISC-V-based domain-specific architecture (DSA), Venus is tailored for 6G edge intelligence scenarios, enabling efficient integration of artificial intelligence and wireless baseband processing to...
📜Zoozve: A Strip-Mining-Free RISC-V Vector Extension with Arbitrary Register Grouping Compilation Support (WIP)
At the 26th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES ‘25), we proposed Zoozve, a novel RISC-V vector extension that eliminates the need for strip-mining in long-vector processing. Zoozve supports arbitrary vector register grouping and features a data-adaptive register allocation strategy, significantly reducing register...
📜A Hierarchical Dataflow-Driven Heterogeneous Architecture for Wireless Baseband Processing
At the 30th Asia and South Pacific Design Automation Conference (ASPDAC ’25), we presented a cache-free, NUMA-based heterogeneous architecture tailored to the cyclical and modular nature of wireless baseband processing (WBP). Leveraging a novel “pack-and-ship” data dispatching strategy and a multi-level dataflow scheduling model, our system improves data locality and...
🗞️UVP Makes It: 5G PBCH MIB Decoded Successfully
On January 1, 2025, our team successfully decoded the Master Information Block (MIB) in the 5G Physical Broadcast Channel (PBCH) using a system based on the UVP architecture in the laboratory. This achievement validates the application value of UVP in practical wireless communication scenarios.
📜A Domain Specific Computing Architecture for Open 6G Baseband Signal Processing
At the ACM Turing Award Celebration Conference 2023 - China (TURC ‘23), we introduced a domain-specific manycore architecture optimized for future 6G baseband signal processing. Built upon RISC-V instruction extensions and a multi-level dataflow programming model, our design achieves moderate performance while offering flexible software programmability. By integrating custom instructions...
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