Research progress
From architecture and tools to applications
Zoozve: flexible vector registers, from compiler to hardware
Arbitrary register grouping connects a RISC-V vector extension, an LLVM backend and a hardware implementation.
Coordinating many-core execution with hardware and software
Offline dependency analysis meets runtime hardware dispatch for heterogeneous many-core systems.
Venusian: a faster path to wireless baseband validation
High-level programming and FPGA-based RISC-V accelerator co-design bring application development and hardware evaluation closer.
A flexible GNSS receiver on the Venus architecture
The ISCAS 2026 demonstration brings Venus architecture research to satellite-navigation reception.
A power-efficient baseband SoC for sensing and communications
The DATE 2026 Late Breaking Results paper reports RISC-V baseband SoC research for multi-standard integrated sensing and communications.
Unlimited Vector Processing for wireless baseband
A RISC-V extension explores flexible vector lengths and register grouping for signal-processing workloads.
Venus connects AI and wireless baseband processing
A programmable RISC-V architecture for communication–AI workloads at the 6G edge.
Zoozve: exploring strip-mining-free vector compilation
The LCTES work-in-progress paper explores arbitrary register grouping and compilation support.
A hierarchical dataflow architecture for wireless baseband
A heterogeneous architecture organizes tasks and data movement around wireless baseband processing.
A programmable architecture for open 6G baseband
A many-core design combines RISC-V extensions with multi-level dataflow programming.
