ACE-Echo 1.0 helps developers estimate the performance of Venus applications. Its cycle-level model is evaluated against RTL for specific cases. That simulator comparison is separate from comparisons between hardware architectures.
ACE-Echo 1.0 timing measurements
The recorded eight-DAG regression used nominal 300 MHz Tile and 150 MHz AXI clocks. The largest absolute DAG-interval error was 0.4633%; the largest individual-task error was 2.2834%. See the complete results and interval definitions.
These measurements are tied to the listed input matrix and model. A small timing error does not establish all-output algorithm correctness, universal cycle-for-cycle equivalence or measured chip energy consumption.
Earlier architecture research
The following benchmarks evaluate earlier architecture configurations. Read them with the corresponding experimental settings and publications; ACE-Echo 1.0 simulator measurements are reported separately above.
Tile-level comparison
Earlier hardware platforms
Vector architecture experiments
PBCH latency breakdown
Read the original context
The academic archive links the project’s architecture publications. The original performance page preserves its full experimental descriptions.